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15
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Answer
DRAM
e^e's.
acJiJ^eK
One-^j^ord-wid^/memory
organization:
tir<»>^ife.H
4^125
+
4x1
=
65
clock
cycles
(2)
Wide
memory
organization
(two-word):
1
+
2x15
+
2x1
=
33
clock
cycle
"
(3)
Interleaved
memory
organization
(four
banks):
1
+
Ix
15
+
4
X
1
=
20
clock
cycles
°
addveri
^
DRAn
~bri3ir\s-fey
(bic^d
ban/c
il?
aJilras
^
Y
ccr-flut
fi
|
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U-k
I
29
tft
^ ^
&9l-fe
^!J
bo.4
f'|_,
Assume
a
memory
system
that
supports
interleaving
either
four
reads
or
four
writes.
Given
the
following
memory
addresses
in
order
as
they
appear
on
the
memory
bus:
3,
9,
17,
2,
51,
37,
13,
4,
8,
41,
67,
10,
which
ones
will
result
in
a
bank
conflict?
Answer
A
bank
conflict
causes
the
memory
system
to
stall
rmtil
the
busy
bank
has
completed
the
prior
operation.
Reference
Bank Bank
Conflict
3
3
No
9
1
No
17
1
Yes
(with
9)
2 2
No
51
3
No
37
1
Yes
(with
17)
13
1
Yes
(with
37)
4
0
No
8
0
Yes
(with
4)
41
1
No
67
3
No
10
2
No
Bo
|21
3a.
3
3
yi
1
n
in
A
8
??
i?
(3
U
4-1
s-
^1
S
41
3
3
m'
access)
(column
access)
°
DRAMU^—5iJ4^6'^FJf^'fil7DSi^SDRAM[^
